Patent Literature 1 discloses a semiconductor device having a so-called chip-on-chip structure formed by bonding a parent chip and a child chip together. Respective power supply and grounding parts of the parent and child chips are electrically isolated from each other. Diodes (protective or parasitic diodes) are connected in reverse between grounding and signal leads and between power supply and signal leads in each chip. For inspecting whether the connection between signal connection bumps is good or not, test probes are attached to the signal connection bump of the parent chip and the grounding connection bump for supplying a grounding potential to the child chip, so as to apply a test voltage thereto, and it is examined whether or not a circuit is formed through the diodes.
Patent Literature 2 discloses a technique concerning a multilayer module constructed by stacking a plurality of chips. This multilayer module has a plurality of stacked chips and a substrate arranged under the plurality of chips. Each chip has mounting pads and inspection conduction pads on its upper face and mounting terminals, inspection conduction terminals electrically connected to the inspection conduction pads, and inspection signal terminals adjacent to the inspection conduction terminals on its lower face. Inspection connectors to connect with the inspection conduction terminals on the lower face of the chip are arranged on the upper face of the substrate, while mounting terminals and inspection conduction terminals are arranged on the lower face of the substrate. In this multilayer module, an inspection pad of the mounted chip and an inspection terminal of a chip to be stacked are connected to each other, and an inspection signal is fed from the inspection terminal of the mounted chip electrically continuous with the inspection pad, so as to perform a continuity test.
Patent Literature 3 discloses a technique concerning a memory system including a plurality of memory modules as respective memory subsystems. In this memory system, which comprises a plurality of DRAM chips stacked on an IO chip and a through-hole electrode connecting each DRAM chip to the IO chip, a system data signal and an inner data signal within each DRAM are converted into each other by the IO chip.
Patent Literature 4 discloses a technique concerning a program such as a CAD tool for estimating a failure position which is a cause of a reaction from a location of the reaction detected by a luminescent microscope or the like and a failure analysis method using the same. This failure analysis method detects light emitted by a transistor formed within a circuit, so as to narrow the location where the circuit fails.